PCB Assembly Service for Computing and Storage

The core requirements for computing center circuit boards are usually as follows:

✅  High signal integrity (≤ 0.5dB insertion loss)

✅  High heat dissipation efficiency (Δ T ＜ 10 ℃/layer)

✅  High density integration (≥ 20 layers)

❌  Low power consumption (power ripple<1%)

❌  Low failure rate (MTBF>100000 hours)

In the production and assembly process, we focus on the following 7 areas:

1. Materials and Design

• High frequency and low loss substrate:

Using Rogers RO4000 series or Panasonic Megtron 6, reduce transmission loss of 10GHz+signal (Df<0.002).

• High density interconnect (HDI):

Use any layer HDI technology with aperture ≤ 0.1mm and line width/spacing ≤ 0.05mm.

• Heat dissipation enhancement:

Metal substrate (aluminum/copper) or embedded copper block for heat dissipation (local temperature reduction of 15-20 ℃).

Multi layer board with integrated heat dissipation through holes (Thermal Via), thermal conductivity>200 W/m • K.

2. Manufacturing process

• Precision machining:

Laser direct imaging (LDI): achieves a line width accuracy of ± 5 μ m and reduces graphic distortion.

Pulse electroplating filling: Ensure high aspect ratio (10:1) micropores are filled without voids.

• Surface treatment:

The high-frequency signal layer uses chemical immersion Ag to reduce signal loss.

The power layer uses ENEPIG, which meets the wear-resistant requirements for multiple insertions and removals.

3. Assembly and welding

• High precision SMT:

Fully automatic SMT equipment (± 15 μ m accuracy) is used to mount 01005 packaged components and BGA (ball pitch 0.35mm).

• Advanced welding technology:

Vacuum reflow soldering: porosity<3% (traditional process is 5-15%), improving the reliability of high-power chips.

Selective welding: Avoid secondary damage to sensitive components caused by high heat.

• Underfill:

Inject epoxy resin into high-density BGA chips to reduce solder joint cracking caused by mechanical stress.

4. Signal and power integrity

• Impedance control:

Differential impedance tolerance of ± 5% requires 3D electromagnetic field simulation optimization (such as HFSS or CST).

• Power layered design:

Adopting a 2N+2 stacked structure (where N is the signal layer), the dedicated power layer reduces ripple (<30mV).

• Decoupling capacitor layout:

Ultra low ESL (equivalent series inductance) capacitors are placed nearby to suppress high-frequency noise.

5. Testing and Verification

• High speed signal testing:

Eye diagram test: The 28Gbps+SerDes signal needs to meet a 20% eye height/width margin.

TDR (Time Domain Reflectance): detects impedance transition points (error<5%).

• Thermal simulation and actual testing:

The infrared thermal imaging device locates hotspots to ensure that the chip junction temperature is less than 85 ℃ (under long-term load).

• Long term aging test:

Operating continuously for 1000 hours in an environment with 85 ℃/85% humidity, the failure rate is less than 0.01%.

6. Reliability and Maintenance

• Redundant design:

The key power module adopts N+1 redundancy and supports hot swappable replacement.

• Seismic resistant structure:

Design reinforcement bars around the installation holes and conduct random vibration testing at 20-2000Hz (IEC 60068-2-64).

• Maintainability:

Modular design supports quick replacement (such as PCIe slot lifespan>100000 insertions and removals).

7. Environmental Protection and Energy Efficiency

• Halogen free materials:

comply with IEC 61249-2-21 standard, reducing the release of toxic substances.

• Energy efficiency optimization:

Power conversion efficiency>96% (80Plus Titanium certification standard).

Copper foil roughness ≤ 1.5 μ m (reduces high-frequency skin effect loss).